1. Field of the Invention
The invention relates to a service switching point having a direct memory access controller used for controlling a data transfer between a data memory and an input/output device.
2. Discussion of the Related Art
Such a service switching point is used, for example, for processing digital data streams of PCM30 systems. When a subscriber device is connected to the service switching point via a so-termed DSV2 connecting line, 2.048 Mbit/s data rates occur. The data streams are subdivided into successive frames, which have each thirty-two time slots consecutively numbered from 0 to 31. Each time slot contains eight bits. The time slots 1 to 15 and 17 to 31 then correspond each to a speech channel. A time slot 0 carries message and synchronization bits. The time slots 16 carry each eight data bits for a signalling channel which is used for transmitting switching information (signalling information). The eight bits of each time slot 16 contain the switching information for two speech channels. The time slots 16 of sixteen successive frames carry the switching information for all 30 speech channels to be switched (IKZ50 signalling).
In order to make it possible to switch an arriving or outgoing 2.048 Mbit/s data stream, the data bits of the signalling channel (time slot 16) of at least 16 successive frames are to be buffered in a data memory. The data memory has a predeterminable storage area for both the incoming and outgoing data streams. An incoming data stream is received by the input device from where the data bits of the signalling channel are transferred to the data memory on a data bus. Furthermore, signalling data stored in the data memory and meant for the outgoing data stream are transferred to the output device on the data bus.
It is known to use a direct memory access controller DMA for controlling the data transfer between an input/output device and a data memory, so as not to burden a processor with this task. The processor can perform other process-internal functions during the data transfer. From U.S. Pat. No. 5,251,303 is known the connection of a direct memory access controller (DMA) for controlling a data transfer between input/output devices and a data memory in digital computers. The direct memory access controller is then used for generating addresses (pointers) for addressing each storage area of the data memory in which the data to be transferred are written or from which they are read.
Before the beginning of a data transfer, the direct memory access controller is to be initialized. On initialization, one address register for a source address and one address register for a target address are put on a start address for each channel of the direct memory access controller, while for each direction of data transfer one channel is provided. The source address addresses the data source, the destination address addresses the data sink. Furthermore, on initialization of the direct memory access controller, the number of data bytes is determined which are to be transferred during one data communication cycle. When a data byte is transferred, a counter of the direct memory access controller is incremented or decremented. If the number of increments or decrements (and thus the respective count) correspond to the number of data bytes to be transferred, predefined at the initialization, a renewed initialization of the direct memory access controller is needed for a further data transfer.
In a service switching point for processing data streams at a data rate of 2.048 Mbit/s, as described above, the successive time slots 16 of the signalling channel have each a 125 .mu.s distance i.e. an initialization of the direct memory access controller is to take place within 125 .mu.s after the last memory cell of the memory area of the data memory has been written/read, in which the data or signalling bits respectively, of the time slot 16 of the incoming or outgoing data stream respectively, are buffered. The initialization of the direct memory access controller is effected with the aid of a processor whose main task is processing the signalling data stored in the data memory. In the case of high data rates, the processor is to effect the initializations of the direct memory access controller in such short distances in time that there is not enough time available for its other tasks, especially, the processing of the signalling data.